Such a transistor is known e.g. from the paper "Analysis of New High-Voltage Bipolar Silicon-on-Insulator Transistor with Fully Depleted Collector" by Torkel Arnborg and Andrej Litwin in IEEE Transactions on Electron Devices, Vol. 42, No. 1, Jan. 1995.
In the known transistor, the breakdown voltage drops very sharply while increasing the substrate voltage in comparison to the emitter voltage for npn transistors and the opposite for pnp transistors. That is due to the fact that an accumulation layer is created under the emitter of the transistor, which accumulation layer for a certain substrate voltage value makes it impossible to fully deplete the collector under the emitter and lock the potential. The breakdown voltage is thus the same as it would be for a vertical transistor with buried layer and an epitaxial layer over it with similar epitaxial layer thickness and doping as the silicon-on-insulator layer, which breakdown is quite low.
Having the same requirements on the breakdown voltage for both npn and pnp transistors implies that the substrate voltage needs to be close to the middle of the applied operational voltage span. That further lowers the highest possible breakdown voltage for the transistor. Also, a soft collector breakdown or punch through may in some cases start just before the potential lock occurs for increasing collector bias.